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A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Feb2013, Vol. 60 Issue 2, p268-278. 11p. - Publication Year :
- 2013
-
Abstract
- This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10^-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm^2 and 0.94 mm^2, respectively, in a 0.13 \mum 1P8M CMOS process. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 60
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 85169697
- Full Text :
- https://doi.org/10.1109/TCSI.2012.2215779