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A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Mar2013, Vol. 60 Issue 3, p557-569. 13p. - Publication Year :
- 2013
-
Abstract
- <?Pub Dtl?>This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precision and high-linearity with moderate area occupation per measurement channel. The architecture is based on a coarse counter and a couple of two-stage interpolators that exploit the cyclic sliding scale technique in order to improve the conversion linearity. The interpolators are based on a new coarse-fine synchronization circuit and a new single-stage Vernier delay loop fine interpolation. In a standard cost-effective 0.35 \mum CMOS technology the TDC reaches a dynamic range of 160 ns, 17.2 ps precision and differential non-linearity better than 0.9% LSB rms. The TDC building block was designed in order to be easily assembled in a multi-channel monolithic TDC chip. Coupled with a SPAD photodetector it is aimed for TCSPC applications (like FLIM, FCS, FRET) and direct ToF 3-D ranging. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 60
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 85920984
- Full Text :
- https://doi.org/10.1109/TCSI.2012.2215737