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A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA.
- Source :
-
IEEE Transactions on Signal Processing . Jun2013, Vol. 61 Issue 11, p2940-2951. 12p. - Publication Year :
- 2013
-
Abstract
- This paper presents a high-throughput decoder architecture for non-binary low-density parity-check (LDPC) codes, where the q-ary sum-product algorithm (QSPA) in the log domain is considered. We reformulate the check-node processing such that an efficient trellis-based implementation can be used, where forward and backward recursions are involved. In order to increase the decoding throughput, bidirectional forward-backward recursion is used. In addition, layered decoding is adopted to reduce the number of iterations based on a given performance. Finally, a message compression technique is used to reduce the storage requirements and hence the area. Using a 90-nm CMOS process, a 32-ary (837,726) LDPC decoder was implemented to demonstrate the proposed techniques and architecture. This decoder can achieve a throughput of 233.53 Mb/s at a clock frequency of 250 MHz based on the post-layout results. Compared to the decoders presented in previous literature, the proposed decoder can achieve the highest throughput based on a similar/better error-rate performance. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 1053587X
- Volume :
- 61
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Signal Processing
- Publication Type :
- Academic Journal
- Accession number :
- 87582119
- Full Text :
- https://doi.org/10.1109/TSP.2013.2256905