The behavioral model of a split capacitor array involved in the successive approximation register ADC and taking into account the effect of parasitic capacitors.

The analysis of the effect of the parasitic capacitors on the split capacitor array digital-to analog converter for use in the successive approximation register analog-to-digital converter is presented. The Verilog-A model of the split capacitor array is developed based on the analysis. The advantages of using this model in the context of the top-down design methodology are considered. [ABSTRACT FROM AUTHOR]