Back to Search
Start Over
Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs.
- Source :
-
IEEE Transactions on Components, Packaging & Manufacturing Technology . Oct2013, Vol. 3 Issue 10, p1720-1730. 11p. - Publication Year :
- 2013
-
Abstract
- In this paper, we analyze the variability in a 3-D clock network designed with single and multiple through-silicon vias and present a post-silicon tuning methodology, called tier adaptive body biasing (TABB), to reduce skew and data path variability in 3-D clock trees. TABB uses specialized on-die sensors to independently detect the process corners of n-channel metal–oxide–semiconductor (nMOS) and p-channel metal–oxide–semiconductor (pMOS) devices and accordingly tune the body biases of nMOS/pMOS devices to reduce the clock skew variability. We also present the system architecture of TABB and circuit techniques for the on-die sensors. Circuit-level simulation and statistical analysis of the TABB architecture in a predictive 45-nm technology demonstrate the effectiveness of TABB in reducing the clock skew variability considering the data path variability in 3-D ICs. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 21563950
- Volume :
- 3
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Components, Packaging & Manufacturing Technology
- Publication Type :
- Academic Journal
- Accession number :
- 90677331
- Full Text :
- https://doi.org/10.1109/TCPMT.2013.2238581