Cite
Design space exploration of on-chip ring interconnection for a CPU–GPU heterogeneous architecture.
MLA
Lee, Jaekyu, et al. “Design Space Exploration of On-Chip Ring Interconnection for a CPU–GPU Heterogeneous Architecture.” Journal of Parallel & Distributed Computing, vol. 73, no. 12, Dec. 2013, pp. 1525–38. EBSCOhost, https://doi.org/10.1016/j.jpdc.2013.07.014.
APA
Lee, J., Li, S., Kim, H., & Yalamanchili, S. (2013). Design space exploration of on-chip ring interconnection for a CPU–GPU heterogeneous architecture. Journal of Parallel & Distributed Computing, 73(12), 1525–1538. https://doi.org/10.1016/j.jpdc.2013.07.014
Chicago
Lee, Jaekyu, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili. 2013. “Design Space Exploration of On-Chip Ring Interconnection for a CPU–GPU Heterogeneous Architecture.” Journal of Parallel & Distributed Computing 73 (12): 1525–38. doi:10.1016/j.jpdc.2013.07.014.