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Providing multiple hard latency and throughput guarantees for packet switching networks on chip.

Authors :
Heisswolf, Jan
König, Ralf
Kupper, Martin
Becker, Jürgen
Source :
Computers & Electrical Engineering. Nov2013, Vol. 39 Issue 8, p2603-2622. 20p.
Publication Year :
2013

Abstract

Abstract: In many-core architectures different distributed applications are executed in parallel. The applications may need hard guarantees for communication with respect to latency and throughput to cope with their constraints. Networks on Chip (NoC) are the most promising approach to handle these requirements in architectures with a large number of cores. Dynamic reservation of communication resources in virtual channel NoCs is used to enable quality of service for concurrent communication. This paper presents a router design supporting best effort and connection-oriented guaranteed service communication. The communication resources are shared dynamically between the two communication schemes. The key contribution is a concept for virtual channel reservation supporting different bandwidth and latency guarantees for simultaneous guaranteed service communication flows. Different to state-of-the-art, the used scheduling approach allows to give hard guarantees regarding throughput and latency. The concept enables to adjust the bandwidth and latency requirements of connections at run-time to cope with dynamically changing application requirements. Due to its distributed reservation process and resource allocation it offers good scalability for many-core architectures. The implementation of a router and the required extension of a network interface to support the proposed concept are presented. The software perspective is discussed. An algorithm is presented that is used to establish guaranteed service connections according to the applications bandwidth requirements. Simulation results are compared to state-of-the-art arbitration schemes and show significant improvements of latency and throughput, e.g. for an MPEG4 application. Synthesis results expose the low area overhead and impact on energy consumption which makes the concepts highly attractive for QoS-constraint many-core architectures. [Copyright &y& Elsevier]

Details

Language :
English
ISSN :
00457906
Volume :
39
Issue :
8
Database :
Academic Search Index
Journal :
Computers & Electrical Engineering
Publication Type :
Academic Journal
Accession number :
92640928
Full Text :
https://doi.org/10.1016/j.compeleceng.2013.06.005