Back to Search
Start Over
Effective Method for Simultaneous Gate Sizing and V th Assignment Using Lagrangian Relaxation.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . Apr2014, Vol. 33 Issue 4, p546-557. 12p. - Publication Year :
- 2014
-
Abstract
- This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than refid="ref1"/ and 12.45% smaller than refid="ref2"/. The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 33
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 95055074
- Full Text :
- https://doi.org/10.1109/TCAD.2014.2305847