FPGA densities hit 20 kgates with pASICs.

Reports on a second-generation family of low-density FPGA, QuickLogic's pASIC 2 series, that offers 3000 up to 20000 usable gates, datapath speeds exceeding 200 MHz and counter speeds that go beyond 150 MHz without increasing chip area or slowing the logic. Three-layer metallization scheme created to achieve denser interconnections for the logic; Design of the pASIC 2 series. INSET: Not the only three-level metal antifuse solution..