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A 7-bit, 1.4 GS/s ADC With Offset Drift Suppression Techniques for One-Time Calibration.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Aug2013, Vol. 60 Issue 8, p1979-1990. 12p. - Publication Year :
- 2013
-
Abstract
- This paper describes a digitally calibrated 7-bit, 1.4 GS/s flash analog-to-digital converter (ADC) implemented in 45-nm CMOS. The proposed offset drift suppression techniques for dynamic comparator and preamplifier make the ADC robust against environmental variation. As a result, once the ADC is calibrated at power up, no more calibration is necessary, even under VDD or temperature variations. The robustness is theoretically and experimentally verified. A calibration algorithm for doubling the ADC accuracy is also presented. The ADC occupies a small area of 0.085 \ mm^2 and dissipates 33.24 mW at 1.4 GS/s from a 1.15 V supply. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 60
- Issue :
- 8
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 95452125
- Full Text :
- https://doi.org/10.1109/TCSI.2013.2256236