Cite
A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell.
MLA
Close, Gael F., et al. “A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 60, no. 6, June 2013, pp. 1521–33. EBSCOhost, https://doi.org/10.1109/TCSI.2012.2220459.
APA
Close, G. F., Frey, U., Morrish, J., Jordan, R., Lewis, S. C., Maffitt, T., BrightSky, M. J., Hagleitner, C., Lam, C. H., & Eleftheriou, E. (2013). A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 60(6), 1521–1533. https://doi.org/10.1109/TCSI.2012.2220459
Chicago
Close, Gael F., Urs Frey, Jack Morrish, Richard Jordan, Scott C. Lewis, Tom Maffitt, M. J. BrightSky, Christoph Hagleitner, C. H. Lam, and Evangelos Eleftheriou. 2013. “A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 60 (6): 1521–33. doi:10.1109/TCSI.2012.2220459.