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High Performance Stereo System for Dense 3-D Reconstruction.
- Source :
-
IEEE Transactions on Circuits & Systems for Video Technology . Jun2014, Vol. 24 Issue 6, p929-941. 13p. - Publication Year :
- 2014
-
Abstract
- 3-D stereo reconstruction, a technique that estimates per-pixel depth in a scene, is still a challenging problem mainly due to some prohibitive factors that limit its performance and computational ability. The aim of this paper is to present a new hardware-efficient disparity map computation, which is based on disparity space image processing using discrete dynamic systems. The hardware architecture of the proposed system was implemented on a high-end field programmable gate array (FPGA) device, offering real-time 3-D reconstruction speeds using a hardware aware architecture based on parallelism and process pipelining. The proposed architecture fulfills the requirements of real-world applications regarding resource usage, frame rates, and disparity resolution, while its implementation on an Altera Stratix IV family FPGA device can extract disparity maps of up to \(\mathbf {1280 \times 1024}\) pixels with up to 128 disparity levels under real-time or near real-time conditions at a clock rate of 168 MHz. Qualitative and quantitative results also demonstrate its performance and improvement over previous hardware-related studies, making our approach a suitable candidate for applications in which timing and processing constraints are critical. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 10518215
- Volume :
- 24
- Issue :
- 6
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems for Video Technology
- Publication Type :
- Academic Journal
- Accession number :
- 96381433
- Full Text :
- https://doi.org/10.1109/TCSVT.2013.2290575