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Optimizing quarter and sub-quarter micron CMOS circuit...
- Source :
-
IEEE Transactions on Electron Devices . Sep97, Vol. 44 Issue 9, p1556. 3p. 4 Graphs. - Publication Year :
- 1997
-
Abstract
- Reports that the experimentally confirmed accurate complementary metal oxide semiconductor (CMOS) gate delay model is applied to the CMOS ring oscillators with interconnect loading. Guidelines in choosing optimum Tox for different interconnect loading, combined with channel length and power supply scaling; Modeling and discussion; Conclusion.
- Subjects :
- *COMPLEMENTARY metal oxide semiconductors
*SEMICONDUCTORS testing
Subjects
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 44
- Issue :
- 9
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 9709280550
- Full Text :
- https://doi.org/10.1109/16.622616