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Design of 65 nm CMOS SRAM for Space Applications: A Comparative Study.
- Source :
-
IEEE Transactions on Nuclear Science . Aug2014 Part 1, Vol. 61 Issue 4, p1575-1582. 8p. - Publication Year :
- 2014
-
Abstract
- We study the design of different 6T and DICE SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 00189499
- Volume :
- 61
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Nuclear Science
- Publication Type :
- Academic Journal
- Accession number :
- 97562934
- Full Text :
- https://doi.org/10.1109/TNS.2014.2319154