Cite
TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs.
MLA
Kim, Dae Hyun, et al. “TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 33, no. 9, Sept. 2014, pp. 1384–95. EBSCOhost, https://doi.org/10.1109/TCAD.2014.2329472.
APA
Kim, D. H., Mukhopadhyay, S., & Lim, S. K. (2014). TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 33(9), 1384–1395. https://doi.org/10.1109/TCAD.2014.2329472
Chicago
Kim, Dae Hyun, Saibal Mukhopadhyay, and Sung Kyu Lim. 2014. “TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems 33 (9): 1384–95. doi:10.1109/TCAD.2014.2329472.