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A Band-Reject Nested-PLL Clock Cleaner Using a Tunable MEMS Oscillator.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Mar2014, Vol. 61 Issue 3, p653-662. 10p. - Publication Year :
- 2014
-
Abstract
- <?Pub Dtl?>This paper presents the Band-Reject Nested-PLL (BRN-PLL) scheme that simultaneously improves filtering of a noisy input signal and relaxes the requirements for the loop bandwidth. As the architecture employs a modified PLL as a divider of another PLL, a stability analysis is presented to demonstrate suitable operation. The BRN-PLL close-to-carrier output noise is dominated by the PFD/CP of the inner PLL and the far-from-carrier output noise is dominated by the LO of the outer PLL. The PFD/CP noise can be reduced by approximately 20 dB when the output is disconnected from the VCO during idle states, and a low noise floor is achieved using a passively biased double-switching pair LC VCO. Additionally, to maintain lower integrated phase noise, the proposed scheme uses a high-Q MEMS-based VCO to effectively smoothen the transition of the response between the two dominant noise sources. Absolute figures equal to -105 dBc/Hz at 1 kHz and -155 dBc/Hz at 10 MHz are measured from a 104 MHz clock-cleaner. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 61
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 98013576
- Full Text :
- https://doi.org/10.1109/TCSI.2013.2284186