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A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Aug2014, Vol. 61 Issue 8, p2466-2472. 7p. - Publication Year :
- 2014
-
Abstract
- This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 \mum CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10^-13 while consuming 82 mW at 10-Gb/s. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 61
- Issue :
- 8
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 98013716
- Full Text :
- https://doi.org/10.1109/TCSI.2014.2309861