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Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Oct2014, Vol. 61 Issue 10, p2978-2986. 9p. - Publication Year :
- 2014
-
Abstract
- The efficiency of power amplifiers (PAs) with a small output power (POUT) for short-range wireless sensor networks is limited by the loss in matching networks. To achieve high efficiency, a new design method which calculates the complicated design parameters in a class-F PA with a merged filter and matching networks is proposed. The design method provides a new quantitative conclusion that reducing both the power supply voltage (VDD) and the impedance transformation ratio increases the efficiency of a PA with a small POUT. Using this result, a dual-VDD scheme is realized to increase the efficiency of a transmitter (TX). At a POUT of -20 dBm, compared with the conventional single-VDD scheme, the drain efficiency (DE) of the PA and the global efficiency (GE) of the TX with the dual-VDD scheme are increased by factors of 2.1 and 1.5, respectively. A PA fabricated by a 40 nm CMOS process achieved a DE of 42% at a POUT of -17 dBm. The TX with the PA achieves the highest GE of 28% at a POUT of -20 dBm and the lowest energy of 36pJ/bit (=36\ \muW@1Mbps with on-off keying) among the published results for TXs. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 61
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 98573220
- Full Text :
- https://doi.org/10.1109/TCSI.2014.2321202