A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration.

A 6-bit 1 GS/s single-channel pipeline ADC using an incomplete settling concept is presented. A background sampling-point calibration is proposed to adjust MDAC sampling point so that low gain and low bandwidth opamp can be utilized to conserve power. The prototype ADC in 65-nm CMOS process exhibits an INL of +0.76/-0.68 LSB and a DNL of +0.72/-0.68 LSB. Its ENOB is 5.25 bits at Nyquist input frequency with the conversion rate of 1 GS/s. It consumes 62 mW including calibration circuit power at 1 V supply and occupies an active chip area of 0.3 mm^2. [ABSTRACT FROM AUTHOR]