VLSI symposium eyes 65-nm logic.

Reports on 65-nanometer technology demonstrations and papers that will be presented at the 2003 VLSI Technology Symposium in June 10-12, 2003, in Kyoto, Japan. Toshiba-Sony paper describing an embedded SRAM technology at 65-nm line widths that achieves a cell size of 0.56 square micron; Motorola-Philips-ST team's presentation of its 65-nm complementary metal oxide semiconductors integration strategy.