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A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Nov2014, Vol. 61 Issue 11, p3278-3287. 10p. - Publication Year :
- 2014
-
Abstract
- This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71-mm^2. With input 10-Gb/s data of a 2^31-1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 \mus. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 61
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 99083033
- Full Text :
- https://doi.org/10.1109/TCSI.2014.2327291