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A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Nov2014, Vol. 61 Issue 11, p3085-3093. 9p. - Publication Year :
- 2014
-
Abstract
- A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490\mum\times 7.4\mum and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18\mum technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 61
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 99083038
- Full Text :
- https://doi.org/10.1109/TCSI.2014.2334852