Cite
Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology.
MLA
Cicalini, Mattia, et al. “Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 Nm CMOS Technology.” Sensors (Basel, Switzerland), vol. 22, no. 1, Dec. 2021. EBSCOhost, https://doi.org/10.3390/s22010121.
APA
Cicalini, M., Piotto, M., Bruschi, P., & Dei, M. (2021). Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology. Sensors (Basel, Switzerland), 22(1). https://doi.org/10.3390/s22010121
Chicago
Cicalini, Mattia, Massimo Piotto, Paolo Bruschi, and Michele Dei. 2021. “Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 Nm CMOS Technology.” Sensors (Basel, Switzerland) 22 (1). doi:10.3390/s22010121.