Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications

Abstract: Open Computing Language (OpenCL) is a high-level language that allows developers to produce portable software for heterogeneous parallel computing platforms. OpenCL is available for a variety of hardware platforms, with compiler support being recently expanded to include Field-Programmable Gate Arrays (FPGAs). This work investigates flexible OpenCL designs for the iterative min-sum decoding algorithm for both symmetric and asymmetric Low-Density Parity Check (LDPC) codes over a range of codeword lengths. The computationally demanding LDPC decoding algorithm offers several forms of parallelism that could be exploited by the Altera-Offline-Compiler (AOC version 15.1) for OpenCL. By starting with the recommended design approaches and optimizing based on experimentation, the highest throughput symmetric LDPC decoder produced a maximum corrected codeword throughput of 68.22 Mbps for 32 decoding iterations at the compiler-selected FPGA clock frequency of 163.88 MHz for a length-2048 (3,6)-regular code. Designs for three of the DOCSIS 3.1 [7] standard asymmetric codewords were investigated and implemented using the AOC. The designs prove that OpenCL on FPGAs can produce high-throughput results for industry-sized asymmetric LDPC codes with significantly shorter design time compared to other custom hardware and software applications.