Cite
A Low Damage Etching Process of Sub-100 nm Platinum Gate Line for III–V Metal–Oxide–Semiconductor Field-Effect Transistor Fabrication and the Optical Emission Spectrometry of the Inductively Coupled Plasma of SF6/C4F8.
MLA
Li, Xu, et al. “A Low Damage Etching Process of Sub-100 Nm Platinum Gate Line for III–V Metal–Oxide–Semiconductor Field-Effect Transistor Fabrication and the Optical Emission Spectrometry of the Inductively Coupled Plasma of SF6/C4F8.” Japanese Journal of Applied Physics, vol. 51, no. 1S, Jan. 2012, p. 1. EBSCOhost, https://doi.org/10.7567/jjap.51.01ab01.
APA
Li, X., Zhou, H., Hill, R. J. W., Holland, M., & Thayne, I. G. (2012). A Low Damage Etching Process of Sub-100 nm Platinum Gate Line for III–V Metal–Oxide–Semiconductor Field-Effect Transistor Fabrication and the Optical Emission Spectrometry of the Inductively Coupled Plasma of SF6/C4F8. Japanese Journal of Applied Physics, 51(1S), 1. https://doi.org/10.7567/jjap.51.01ab01
Chicago
Li, Xu, Haiping Zhou, Richard J. W. Hill, Martin Holland, and Iain G. Thayne. 2012. “A Low Damage Etching Process of Sub-100 Nm Platinum Gate Line for III–V Metal–Oxide–Semiconductor Field-Effect Transistor Fabrication and the Optical Emission Spectrometry of the Inductively Coupled Plasma of SF6/C4F8.” Japanese Journal of Applied Physics 51 (1S): 1. doi:10.7567/jjap.51.01ab01.