Proposal for a graphene-based all-spin logic gate.

In this work, we present a graphene-based all-spin logic gate (G-ASLG) that integrates the functionalities of perpendicular anisotropy magnetic tunnel junctions (p-MTJs) with spin transport in graphene-channel. It provides an ideal integration of logic and memory. The input and output states are defined as the relative magnetization between free layer and fixed layer of p-MTJs. They can be probed by the tunnel magnetoresistance and controlled by spin transfer torque effect. Using lateral non-local spin valve, the spin information is transmitted by the spin-current interaction through graphene channels. By using a physics-based spin current compact model, the operation of G-ASLG is demonstrated and its performance is analyzed. It allows us to evaluate the influence of parameters, such as spin injection efficiency, spin diffusion length, contact area, the device length, and their interdependence, and to optimize the energy and dynamic performance. Compared to other beyond-CMOS solutions, longer spin information transport length (~μm), higher data throughput, faster computing speed (~ns), and lower power consumption (~μA) can be expected from the G-ASLG. [ABSTRACT FROM AUTHOR]