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A Multibit Delta–Sigma Modulator With Double Noise-Shaped Segmentation.
- Source :
- IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Mar2015, Vol. 62 Issue 3, p241-245, 5p
- Publication Year :
- 2015
-
Abstract
- This brief proposes a low-power architecture for a discrete-time (DT) delta–sigma modulator to take full advantages of increased quantization levels. In the proposed architecture, noise-shaped segmentation is applied to both the quantizer and the feedback digital-to-analog converter to maintain a high resolution and a high linearity and, at the same time, keep the hardware complexity low. This leads to a significantly reduced output swing of the integrator to minimize the slewing-related distortion in a DT implementation. The resulting uniform linear settling behavior can tolerate a relatively large settling error without degrading the performance, which greatly relaxes the bandwidth requirement of the op-amp design. The reduced output swing also allows the use of low-gain amplifiers, which is particularly attractive for an advanced technology in which the intrinsic gain of the transistor is degraded. The proposed architecture is analyzed and verified through simulation. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15497747
- Volume :
- 62
- Issue :
- 3
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part II: Express Briefs
- Publication Type :
- Academic Journal
- Accession number :
- 101302396
- Full Text :
- https://doi.org/10.1109/TCSII.2014.2368261