Cite
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.
MLA
Manem, H., et al. “Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 59, no. 5, May 2012, pp. 1051–60. EBSCOhost, https://doi.org/10.1109/TCSI.2012.2190665.
APA
Manem, H., Rajendran, J., & Rose, G. S. (2012). Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 59(5), 1051–1060. https://doi.org/10.1109/TCSI.2012.2190665
Chicago
Manem, H., J. Rajendran, and G. S. Rose. 2012. “Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 59 (5): 1051–60. doi:10.1109/TCSI.2012.2190665.