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Vertical GAAFETs for the Ultimate CMOS Scaling.

Authors :
Yakimets, Dmitry
Eneman, Geert
Schuddinck, Pieter
Bao, Trong Huynh
Bardon, Marie Garcia
Raghavan, Praveen
Veloso, Anabela
Collaert, Nadine
Mercha, Abdelkarim
Verkest, Diederik
Thean, Aaron Voon-Yew
De Meyer, Kristin
Source :
IEEE Transactions on Electron Devices; May2015, Vol. 62 Issue 5, p1433-1439, 7p
Publication Year :
2015

Abstract

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189383
Volume :
62
Issue :
5
Database :
Complementary Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
102288487
Full Text :
https://doi.org/10.1109/TED.2015.2414924