Back to Search
Start Over
A self-aligned gate GaN MOSFET using an ICP-assisted low-temperature Ohmic process.
- Source :
- Semiconductor Science & Technology; Jul2015, Vol. 30 Issue 7, p1-1, 1p
- Publication Year :
- 2015
-
Abstract
- We report a new approach in fabricating a self-aligned gate GaN MOSFET. The fabrication technique is based on a double-layer photoresist (PR) and low-temperature-Ohmic formation process assisted by an inductively coupled plasma (ICP) dry etching process. In this process, the active region was automatically defined by the combination of a subsequently developed positive PR and the existing negative PR pattern. The Al Ohmic electrodes on the ICP-treated active region were formed by a lift-off process followed by 500 °C N<subscript>2</subscript> 1 min annealing. The specific contact resistance of 4.8 × 10<superscript>−6</superscript>Ω cm<superscript>2</superscript> was obtained in this process. Operation up to a gate bias of 30 V was confirmed. The maximum output current of 98 mA mm<superscript>−1</superscript> and field-effect mobility of 110 cm<superscript>2</superscript> V<superscript>−1</superscript> s<superscript>−1</superscript> were observed in the device with a gate length of 4 μm. Some non-ideal effects in this device, including the negative threshold voltage, larger off-state leakage and unsaturated on-state drain current, were also observed and analyzed. Some possible ways to improve the performance of the device were proposed. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 02681242
- Volume :
- 30
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- Semiconductor Science & Technology
- Publication Type :
- Academic Journal
- Accession number :
- 103360217
- Full Text :
- https://doi.org/10.1088/0268-1242/30/7/075003