A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

MLA

Dickson, Timothy O., et al. “A 1.4 PJ/Bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 Nm SOI CMOS Technology.” IEEE Journal of Solid-State Circuits, vol. 50, no. 8, Aug. 2015, pp. 1917–31. EBSCOhost, https://doi.org/10.1109/JSSC.2015.2412688.

APA

Dickson, T. O., Liu, Y., Rylov, S. V., Agrawal, A., Kim, S., Hsieh, P.-H., Bulzacchelli, J. F., Ferriss, M., Ainspan, H. A., Rylyakov, A., Parker, B. D., Beakes, M. P., Baks, C., Shan, L., Kwark, Y., Tierno, J. A., & Friedman, D. J. (2015). A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE Journal of Solid-State Circuits, 50(8), 1917–1931. https://doi.org/10.1109/JSSC.2015.2412688

Chicago

Dickson, Timothy O., Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, et al. 2015. “A 1.4 PJ/Bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 Nm SOI CMOS Technology.” IEEE Journal of Solid-State Circuits 50 (8): 1917–31. doi:10.1109/JSSC.2015.2412688.