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Analysis of Partial Bias Schemes for the Writing of Crossbar Memory Arrays.
- Source :
- IEEE Transactions on Electron Devices; Sep2015, Vol. 62 Issue 9, p2845-2849, 5p
- Publication Year :
- 2015
-
Abstract
- Partial bias schemes reduce the disturbance during the writing of crossbar arrays (CBAs). Detailed analysis of two partial bias schemes is presented in this paper: 1) 1/2 bias scheme for low-power operation and 2) 1/3 bias scheme for high-performance (i.e., high Vdd) operation. With partial bias schemes, a sneak leakage reversal phenomenon may occur due to line-resistance-induced voltage degradation, which provides a measure of voltage driving range along access lines. Voltage dividing effect of selector devices reduces disturbance in CBAs and leads to similar writing voltage margin in both bias schemes. Matching a proper partial bias scheme with the selector device choice optimizes the performance of CBAs. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 62
- Issue :
- 9
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 109065840
- Full Text :
- https://doi.org/10.1109/TED.2015.2448592