Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors.

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-g_m), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si3N4, Rapid Thermal Chemical Vapor Deposition Si₃N₄, and Atomic Layer Deposition (ALD) Al₂O₃) for AlGaN/GaN Metal-Insulator- Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (D_it), the amount of border traps, and the threshold voltage (V_TH) shift during a positive gate bias stress can be obtained. The results show that the V_TH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the V_TH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract D_it needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the g_m dispersion commonly attributed to border traps might be influenced by interface states. [ABSTRACT FROM AUTHOR]