Fabrication and electrical characteristics of a novel interposer with polymer liner and silicon pillars with ultra-low-resistivity as through-silicon-vias (TSVs) for 2.5D/3D applications.

Motivated by the desire of process simplicity and feasibility for 2.5D/3D integration, a novel interposer technique with polymer liner and silicon pillars of ultra-low-resistivity as through-silicon-vias (TSVs) is proposed in this paper. Silicon pillars with ultra-low-resistivity, instead of conventionally electroplating copper posts, are utilized as vertical via conductors, and low-k polymer Benzocyclobutene, other than silicon dioxide (SiO), is used to form liners. Fabrication techniques and electrical characteristics of the proposed interposer are illustrated. Test vehicles are successfully fabricated and their electrical characteristics including DC resistance and leakage current are measured. The results show that the DC resistances of the proposed TSVs are averaged at 5.94, 2.68 and 1.72 Ω for silicon pillars with diameters of 10, 20 and 30 μm respectively. Also, with a DC bias voltage of 10 V, the leakage current between TSV to silicon substrate is as low as 6.79 pA. These elementary results illustrate the simplicity, feasibility and high reliability of the proposed interposer structure. [ABSTRACT FROM AUTHOR]