A 60Gb/s 173mW receiver frontend in 65nm CMOS technology.

MLA

Han, Jaeduk, et al. “A 60Gb/s 173mW Receiver Frontend in 65nm CMOS Technology.” 2015 Symposium on VLSI Circuits (VLSI Circuits), Jan. 2015, pp. C230–31. EBSCOhost, https://doi.org/10.1109/VLSIC.2015.7231268.

APA

Han, J., Lu, Y., Sutardja, N., Jung, K., & Alon, E. (2015). A 60Gb/s 173mW receiver frontend in 65nm CMOS technology. 2015 Symposium on VLSI Circuits (VLSI Circuits), C230–C231. https://doi.org/10.1109/VLSIC.2015.7231268

Chicago

Han, Jaeduk, Yue Lu, Nicholas Sutardja, Kwangmo Jung, and Elad Alon. 2015. “A 60Gb/s 173mW Receiver Frontend in 65nm CMOS Technology.” 2015 Symposium on VLSI Circuits (VLSI Circuits), January, C230–31. doi:10.1109/VLSIC.2015.7231268.