A SAR ADC With a MOSCAP-DAC.

The linearity of the vast majority of the ADC topologies is limited by the linearity of the circuit elements employed in their design, such as resistors and capacitors. This paper presents a charge-mode SAR ADC architecture that uses only highly non-linear metal-oxide-semiconductor capacitors (MOSCAPs) as the DAC capacitance elements. The non-linearity of the MOSCAPs is exploited to improve the tolerance of the ADC to comparator offset and noise. The architecture employs local voltage boosting and a new boost-and-bootstrap switch to allow operation with an over-rails input range. A 9 bit prototype is fabricated in a 0.13 \;\upmu\textm CMOS process and operates with a supply voltage of 0.6 V, handling a differential input range of 1.7\; \textV_\textpp. The prototype achieves an effective number of bits (ENOB) larger than 8.5 for a temperature range of $-40$ to 85°C, despite the strong dependency of MOSCAPs to temperature. Operating at 1 MSps, the prototype consumes 2.78 \;\upmu\text{W}, leading to a figure of merit (FoM) of 7.8 fJ/conversion-step. [ABSTRACT FROM PUBLISHER]