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Dynamic positive feedback source-coupled logic (D-PFSCL).
- Source :
- International Journal of Electronics; Oct2016, Vol. 103 Issue 10, p1626-1638, 13p
- Publication Year :
- 2016
-
Abstract
- This paper presents dynamic positive feedback source-coupled logic (D-PFSCL) style which is derived from positive feedback source-coupled logic (PFSCL). The proposed logic style uses dynamic current source in contrast to constant current source of PFSCL to attain lower power consumption. Two techniques for D-PFSCL style-based multistage applications are suggested. Several D-PFSCL gates are simulated and compared with the respective PFSCL counterparts through SPICE simulations by using Taiwan semiconductor manufacturing company 0.18 µm CMOS technology parameters. A maximum power reduction of 84% is achieved for D-PFSCL gates. The effect of process variation on the power consumption of the D-PFSCL gates shows a maximum variation factor of 1.5 between the best and the worst cases. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 00207217
- Volume :
- 103
- Issue :
- 10
- Database :
- Complementary Index
- Journal :
- International Journal of Electronics
- Publication Type :
- Academic Journal
- Accession number :
- 116710162
- Full Text :
- https://doi.org/10.1080/00207217.2016.1138519