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A capacitorless low-dropout regulator with enhanced slew rate and 4.5- $$\upmu \hbox {A}$$ quiescent current.

Authors :
Yeo, Jaejin
Javed, Khurram
Lee, Jaeseong
Roh, Jeongjin
Park, Jae-Do
Source :
Analog Integrated Circuits & Signal Processing; Jan2017, Vol. 90 Issue 1, p227-235, 9p
Publication Year :
2017

Abstract

In this paper, an output-capacitorless, low-dropout (LDO) voltage regulator with excellent load regulation and fast recovery time was designed using two amplifiers, which provided high gain, high bandwidth (HBW), and high slew rate (HSR). In addition, a one-shot current boosting (OSCB) circuit was added for current control to charge and discharge the parasitic capacitance at the power transistor gate during the load-current transition to improve the response time. The experimental results show that the proposed LDO regulator consumes a quiescent current of only 4.5 $$\upmu \hbox {A}$$ and can deliver a maximum load current of 200 mA, while regulating the output voltage at $${\text {1\,V}}$$ with a 1.2 V power supply. We experimentally verified that for a current transition from 0.1 to 200 mA, the undershoot and overshoot voltages were 260 and $${\text {190\,mV}}$$ , with recovery times of only 0.8 and 0.85 $${\upmu }\hbox {s}$$ , respectively. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
09251030
Volume :
90
Issue :
1
Database :
Complementary Index
Journal :
Analog Integrated Circuits & Signal Processing
Publication Type :
Academic Journal
Accession number :
120548626
Full Text :
https://doi.org/10.1007/s10470-016-0869-z