Linear relationship ADC with complimentary switch-based bootstrapped sample and hold circuit.

This paper presents the design, fabrication and tested results of an analogue-to-digital converter (ADC) using linear relationship ratio of comparator and resolution. An original N-bit flash architecture uses 2N−1 comparators (N = resolution), while the proposed architecture uses only N comparators for N-bit making it a linear relationship design. This paper also deals with the design of sample and hold circuit that utilises clock bootstrapping technique which allows sampling at peak voltages and helps in minimising charge injection errors, attaining 125 µV for the proposed design. The proof of concept of 4-bit prototype ADC using 1P−2M is fabricated using AMIS 500 nm CMOS C5X technology and the experimental results at a sampling rate of 800 MS/s reveal an effective no. of bit of 3.34 bits, signal-to-noise ratio of 24.44 dB and differential non-linearity and integral non-linearity of 0.42 and 0.40, respectively. The converter consumes 7 mW power when operated on 2.5 V supply and occupies 0.014 mm2chip area. [ABSTRACT FROM AUTHOR]