A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS.

This paper presents an energy-efficient face detection and recognition processor aimed at mobile applications. The algorithmic optimizations including hybrid search scheme for face detection significantly reduce computational complexity and architecture modification such as feature memory segmentation and further reduce energy consumption. We utilize characteristics of the implemented algorithm and propose a 5T SRAM design heavily optimized for mostly-read operations. Systematic reset and write schemes allow for reliable data write operation. The 5T SRAM reduces the cell area by 7.2% compared to a conventional 6T bit cell in logic rule while significantly improving read margin and voltage scalability due to a decoupled read path. The fabricated processor consumes only 23 mW while processing both face detection and recognition in real time at 5.5 frames/s throughput. [ABSTRACT FROM PUBLISHER]