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Normally-Off LPCVD-SiNx/GaN MIS-FET With Crystalline Oxidation Interlayer.
- Source :
- IEEE Electron Device Letters; Jul2017, Vol. 38 Issue 7, p929-932, 4p
- Publication Year :
- 2017
-
Abstract
- Developing effective technique to protect the etched- GaN surface from the degradation in a high-temperature (i.e., at ~ 780°C) process, such as low-pressure chemical vapor deposition (LPCVD), is essential for fabricating normally-off GaN MIS-FETs with high-quality dielectric/GaN interface and highly reliable gate dielectric. In this letter, we developed an approach of obtaining such a protection layer using oxygen-plasma treatment followed by in situ annealing prior to the LPCVD-SiNx deposition. A sharp and stable crystalline oxidation interlayer (COIL) between the LPCVD-SiNx and etched-GaN was successfully formed. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a VTH of 1.15 V, small on-resistance, small hysteresis, and thermally stable VTH . [ABSTRACT FROM AUTHOR]
- Subjects :
- MISFET (Transistors)
CHEMICAL vapor deposition
OXIDATION
Subjects
Details
- Language :
- English
- ISSN :
- 07413106
- Volume :
- 38
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- IEEE Electron Device Letters
- Publication Type :
- Academic Journal
- Accession number :
- 123805520
- Full Text :
- https://doi.org/10.1109/LED.2017.2707473