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Time-Domain Arithmetic Logic Unit With Built-In Interconnect.
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Oct2017, Vol. 25 Issue 10, p2828-2841, 14p
- Publication Year :
- 2017
-
Abstract
- This paper describes a low-power 1-GHz 4-bit time-domain arithmetic logic unit (ALU) targeting hardware accelerator. This ALU relies on the time-domain computation based on digital-to-time converter, digitally controlled oscillator, time-to-digital converter, and successive approximation register analog-to-digital converter. The interconnect bandwidth limitation addressed by the time-domain and voltage-domain encoding to improve the spectrum efficiency by $8\times $ . Encoder and decoders are part of the computation, and that results in 1-GHz operational speed in 65-nm CMOS consuming 17.75 mW only. Compared to the conventional approach, the proposed time-domain computation achieves significantly lower power and latency for similar area and resolution. [ABSTRACT FROM AUTHOR]
- Subjects :
- TIME-domain analysis
ELECTRIC potential
DECODERS (Electronics)
Subjects
Details
- Language :
- English
- ISSN :
- 10638210
- Volume :
- 25
- Issue :
- 10
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Publication Type :
- Academic Journal
- Accession number :
- 125421922
- Full Text :
- https://doi.org/10.1109/TVLSI.2017.2724600