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A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error.
- Source :
- IEEE Journal of Solid-State Circuits; Nov2017, Vol. 52 Issue 11, p3081-3094, 14p
- Publication Year :
- 2017
-
Abstract
- A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The dc–dc converter achieves 93% peak efficiency for Vi= 2 V and Vo= 1.6 V. [ABSTRACT FROM AUTHOR]
- Subjects :
- CONVERTERS (Electronics)
PULSE width modulation transformers
ELECTRIC circuits
Subjects
Details
- Language :
- English
- ISSN :
- 00189200
- Volume :
- 52
- Issue :
- 11
- Database :
- Complementary Index
- Journal :
- IEEE Journal of Solid-State Circuits
- Publication Type :
- Academic Journal
- Accession number :
- 125951854
- Full Text :
- https://doi.org/10.1109/JSSC.2017.2744618