A Third-Order MASH $\Sigma \Delta $ Modulator Using Passive Integrators.

This paper presents a MASH \Sigma \Delta \textM using only passive integrators and simple differential pairs as low-gain blocks. Instead of high-gain power hungry op-amps it uses more processing gain from the comparator (1-bit quantizer) as a part of the loop gain. The proposed approach allows the design of a continuous-time, 2–1 MASH \Sigma \Delta \textM in a 65-nm CMOS technology occupying an area of just 0.027 mm2. Measurement results show that the modulator achieves a peak SNR/SNDR of 76/72.2 dB and a DR of 77 dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW with 1 V supply. The proposed \Sigma \Delta \textM achieves a Walden figures of merit (FoM) of 23.6 fJ/level and a Schreier FOM of 170 dB. [ABSTRACT FROM AUTHOR]