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Analytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs.
- Source :
- IEEE Transactions on Electron Devices; Dec2017, Vol. 64 Issue 12, p5274-5278, 5p
- Publication Year :
- 2017
-
Abstract
- An analytical model of parasitic capacitancein inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness (Tiox) and inserted-oxide recess (Trec), is shown using the proposed model and TCAD simulations. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 64
- Issue :
- 12
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 127950418
- Full Text :
- https://doi.org/10.1109/TED.2017.2761984