Effects of the Variation of V\text {GS} Sweep Range on the Performance of Negative Capacitance FETs.

We report the first investigation of the impacts of gate voltage sweep range V\text {GS,range} on the performance of negative capacitance (NC) transistors. As V\text {GS,range} is reduced, NC GeSn pFETs generally exhibit an increased hysteresis or a transition from non-hysteretic to hysteretic, and show a degradation of I\text {DS} . This is due to the reduction of the ratio of remnant polarization P\text {r} to coercive field E\text {c} with the reduced voltage across the HZO. Interestingly, however, some NC devices show a negligible impact of V\text {GS,range} on hysteresis and I\text {DS} . The NC transistor demonstrates a stable hysteresis in 139–149 mV range and the improved SS and I\text {DS} over the control device, with a reduced V\text {GS,range} of 0.5 to −0.5 V. To obtain device performance independent of V\text {GS,range} , the ratio of P\text {r}/{E}\text {c} of the HZO needs to stabilize in a very small V\text {GS,range} . [ABSTRACT FROM AUTHOR]