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Effects of the Variation of V\text {GS} Sweep Range on the Performance of Negative Capacitance FETs.

Authors :
Zhou, Jiuren
Han, Genquan
Li, Jing
Liu, Yan
Peng, Yue
Zhang, Jincheng
Sun, Qing-Qing
Zhang, David Wei
Hao, Yue
Source :
IEEE Electron Device Letters; Apr2018, Vol. 39 Issue 4, p618-621, 4p
Publication Year :
2018

Abstract

We report the first investigation of the impacts of gate voltage sweep range V\text {GS,range} on the performance of negative capacitance (NC) transistors. As V\text {GS,range} is reduced, NC GeSn pFETs generally exhibit an increased hysteresis or a transition from non-hysteretic to hysteretic, and show a degradation of I\text {DS} . This is due to the reduction of the ratio of remnant polarization P\text {r} to coercive field E\text {c} with the reduced voltage across the HZO. Interestingly, however, some NC devices show a negligible impact of V\text {GS,range} on hysteresis and I\text {DS} . The NC transistor demonstrates a stable hysteresis in 139–149 mV range and the improved SS and I\text {DS} over the control device, with a reduced V\text {GS,range} of 0.5 to −0.5 V. To obtain device performance independent of V\text {GS,range} , the ratio of P\text {r}/{E}\text {c} of the HZO needs to stabilize in a very small V\text {GS,range} . [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
07413106
Volume :
39
Issue :
4
Database :
Complementary Index
Journal :
IEEE Electron Device Letters
Publication Type :
Academic Journal
Accession number :
128664311
Full Text :
https://doi.org/10.1109/LED.2018.2810075