Improving Time-Efficiency of Fault-Coverage Simulation for MOS Analog Circuit.

In analog fault simulation, the number one challenge is that simulation time could grow rapidly and become prohibitive as the circuit size becomes large. This paper proposes a systematic method to significantly improve the time efficiency in estimating the fault coverage for analog fault simulation. In the proposed method, a circuit under test (CUT) is first partitioned into independent sub-circuits. This is accomplished through mapping the circuit into a graph, decomposing the graph into strongly connected components (SCCs), and generating a sub-circuit for each SCC. The impacts of potential faults directly entering a sub-circuit are then simulated and recorded using the sub-circuits, which is expected to be much more time efficient than fault simulation using the whole circuit, which is much larger in size. Finally, the fault detectability at the given test points is evaluated based on the fault impacts and sensitivity among different sub-circuits. As a first step toward quick estimation of fault coverage, this paper focuses on dc tests. Simulation results show that the fault coverage of dc tests can be estimated sufficiently accurately with simulation time being reduced by 10X for the benchmark circuit, or by approximately the number of SCCs. For a much larger circuit, the number of SCCs is expected to be much larger and the time-saving factor will be much larger. [ABSTRACT FROM PUBLISHER]