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Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect.

Authors :
Wan, Wenbo
Lou, Haijun
Xiao, Ying
Lin, Xinnan
Source :
IEEE Transactions on Electron Devices; May2018, Vol. 65 Issue 5, p1873-1879, 7p
Publication Year :
2018

Abstract

In this paper, the charge-plasma structure over the source/drain region is incorporated into a dopingless junctionless transistor for obtaining the superior immunity of line edge roughness (LER). An optimized on/off current ratio is observed by using numerical simulations. It is also demonstrated that the proposed charge-plasma junctionless transistor (CP-JLT) is insensitive to the variation of LER magnitude. We further reveal the physics that LER affects the electrical characteristics of CP-JLT. Channel minimal width position variation and channel width variation are put forward to explore the impact of LER for the first time. It is observed that the LER affects the ${I}_{\text {ON}}$ of CP-JLT due to the changes of the source width caused by channel minimal width position variation, whereas the LER affects the ${I}_{\text {OFF}}$ , SS, and ${V}_{\text {th}}$ mainly through channel width variation. It is thus proved to be a helpful guide to suppress the LER variation of CP-JLT. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189383
Volume :
65
Issue :
5
Database :
Complementary Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
129949395
Full Text :
https://doi.org/10.1109/TED.2018.2812241