Topology optimization and Monte Carlo multithreading simulation for fault-tolerant nanoarrays.

Nanocomputation based on emerging devices is becoming a major subject of study as a possible alternative to CMOS. These new technologies are highly defective due to the immaturity of the processes. It is extremely important then for both the technologists and the application engineers to have feedbacks on the impact on the circuit of such defectivity. The current scenario, though, evidences a complete lack of algorithms and tools for analyzing these kinds of circuits fault tolerance as well as for designing defect-tolerant circuits. This paper presents an unprecedented CAD ensemble. I) FaTToR, an algorithm for optimizing nanoarray-based circuits tolerance to defects. II) ToPoliNano based on a multithreading Monte Carlo switch-level simulation engine, a CAD for thoroughly analyzing the circuit defect tolerance against defect distributions derived by fabrication processes. Results are demonstrated in terms of output error rate and yield for nanoarray-based circuits of medium complexity. Several defect distributions are used as inputs for both FaTToR optimization and ToPoliNano validation. Our contributions represent a fundamental step forward both in terms of design automation methodology and in terms of specific feedbacks on the technology here studied. The approach is general and can be adopted to several other emerging technologies based on regular fabrics [ABSTRACT FROM AUTHOR]