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From Design to Test: A High-Speed PRBS.

Authors :
Zhu, Kehan
Saxena, Vishal
Source :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Oct2018, Vol. 26 Issue 10, p2099-2107, 9p
Publication Year :
2018

Abstract

A full-rate parallel pseudo random bit sequence (PRBS)-9 is systematically designed in the IBM 130-nm six-level metalization SiGe BiCMOS process with 2.5/3.3-V dual power supplies for the application of testing high-speed interconnects. The PRBS length and the phase difference between channels are studied using the methods of autocorrelation and cross correlation, respectively. The parallel PRBS streams can be used as stimuli for a serializer, and the autocorrelation method can be applied as a PRBS checker. It can also be used as stimuli for a four-level pulse amplitude modulation-4 signaling format transmitter with the least correlation between the LSB and the MSB by choosing the appropriate channel combinations. Two prototype boards are designed to test the PRBS along with an on-chip type-II third-order charge-pump phase-locked loop. Signal integrity issues are investigated. Finally, the PRBS has been demonstrated at board level with nonreturn-to-zero format operating at more than 10 Gb/s. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
10638210
Volume :
26
Issue :
10
Database :
Complementary Index
Journal :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Publication Type :
Academic Journal
Accession number :
132098775
Full Text :
https://doi.org/10.1109/TVLSI.2018.2834373